Decimal Floating Point Square-Root Using SRT Algorithm

Given the popularity of decimal arithmetic, hardware implementation of decimal operations has been a hot topic in the recent decade. The square-root can be implemented as an instruction, directly in hardware, which improves performance of the decimal floating-point unit in the processors. This invention, with the intention of reducing the latency of the decimal square-root operation while maintaining a reasonable cost, proposes an SRT algorithm and the corresponding hardware architecture to compute the decimal square-root.